Systems And Methods for Exposing A Current Processor Instruction Upon Exiting A Virtual Machine

ABSTRACT

Described systems and methods enable a host system to efficiently perform computer security activities, when operating in a hardware virtualization configuration. A processor is configured to generate a VM suspend event (e.g., a VM exit or a virtualization exception) when software executing within a guest VM performs a memory access violation. In some embodiments, the processor is further configured to save disassembly data determined for the processor instruction which triggered the VM suspend event to a special location (e.g., a specific processor register) before generating the event. Saved disassembly data may include the contents of individual instruction encoding fields, such as Prefix, Opcode, Mod R/M, SIB, Displacement, and Immediate fields on Intel® platforms.

RELATED APPLICATIONS

This application claims the benefit of the filing date of U.S.provisional patent application No. 62/038,476, filed on Aug. 18, 2014,entitled “Systems And Methods for Exposing A Current ProcessorInstruction Upon Exiting A Virtual Machine”, the entire contents ofwhich are incorporated by reference herein.

BACKGROUND

The invention relates to computer security, and in particular toperforming computer security operations in hardware virtualizationconfigurations.

Malicious software, also known as malware, affects a great number ofcomputer systems worldwide. In its many forms such as computer viruses,worms, rootkits, and spyware, malware presents a serious risk tomillions of computer users, making them vulnerable to loss of data andsensitive information, identity theft, and loss of productivity, amongothers.

Modern computing applications often employ hardware virtualizationtechnology to create simulated computer environments known as virtualmachines (VM), which behave in many ways as physical computer systems.In applications such as server consolidation andinfrastructure-as-a-service, several virtual machines may runsimultaneously on the same computer system, sharing the hardwareresources among them, thus reducing investment and operating costs. Eachvirtual machine may run its own operating system and/or software,separately from other virtual machines. Due to the steady proliferationof computer security threats such as malware and spyware, each suchvirtual machine potentially requires protection.

Some security solutions protect a virtual machine by monitoring themanner in which guest processes executing within the protected VM accessmemory, to identify potential malicious activity. In one example, acomputer security program may configure the processor to generate aninternal event (e.g., an exception or a VM exit event) when an attemptis made to write to, or execute code from, a specific region of memory,e.g. a region of memory used by a guest process. Such processor eventstypically suspend the execution of the current thread and switch theprocessor to executing an event handler routine, which may form part ofthe computer security program. The computer security program may thusdetect an attempt to access memory in a manner which may be indicativeof malware. After analyzing the event, the computer security program mayemulate the processor instruction which was under execution when theevent occurred, and may return execution to the original thread. Suchmethods are generically known in the art as trap-and-emulate.

Conventional trap-and-emulate methods may place a substantialcomputational burden on the host computer system, potentially impactinguser experience and productivity. Therefore, there is considerableinterest in developing efficient computer security systems and methodssuitable for virtualization environments.

SUMMARY

According to one aspect, a host system comprises at least one hardwareprocessor configured to execute a virtual machine and a computersecurity program. The at least one processor is further configured todetermine whether executing a guest instruction within the virtualmachine causes a violation of a memory access permission. In response,when executing the guest instruction causes the violation, the at leastone hardware processor is further configured to write a part of amachine code representation of the guest instruction to a predeterminedlocation accessible to the computer security program, to suspend theexecution of the guest instruction, and in response to suspending theexecution of the guest instruction, switch to executing the computersecurity program, wherein the computer security program is configured todetermine whether the violation is indicative of a computer securitythreat.

According to another aspect, a method of protecting a host system fromcomputer security threats, the method comprises, in response toreceiving a guest instruction for execution, employing at least onehardware processor of the host system to determine whether executing theguest instruction causes a violation of a memory access permission,wherein the guest instruction executes within a virtual machine exposedby the host system. The method further comprises, in response todetermining whether the guest instruction causes the violation, whenexecuting the guest instruction causes the violation, employing the atleast one hardware processor to write a part of a machine coderepresentation of the guest instruction to a predetermined locationaccessible to the computer security program, and employing the at leastone hardware processor to suspend the execution of the guestinstruction. The method further comprises, in response to suspending theexecution of the guest instruction, switching to executing a computersecurity program configured to determine whether the violation isindicative of a computer security threat.

According to another aspect, at least one hardware processor of a hostsystem is configurable, in response to receiving a guest instruction forexecution, to determine whether executing the guest instruction causes aviolation of a memory access permission, wherein the guest instructionexecutes within a guest virtual machine exposed by the host system. Theat least one hardware processor is further configurable, in response todetermining whether the guest instruction causes the violation, whenexecuting the guest instruction causes the violation, to write a part ofa machine code representation of the guest instruction to apredetermined location accessible to the computer security program, tosuspend the execution of the guest instruction, and in response tosuspending the execution of the guest instruction, to switch toexecuting a computer security program, wherein the computer securityprogram is configured to determine whether the violation is indicativeof a computer security threat.

According to another aspect, a non-transitory computer-readable mediumstores instructions which, when executed by at least one hardwareprocessor of a host system, cause the host system to form a computersecurity program configured to determine whether a violation of a memoryaccess permission is indicative of a computer security threat. The atleast one hardware processor is configurable, in response to receiving aguest instruction for execution, to determine whether executing theguest instruction causes the violation, wherein the guest instructionexecutes within a virtual machine exposed by the host system. The atleast one hardware processor is further configurable, in response todetermining whether the guest instruction causes the violation, whenexecuting the guest instruction causes the violation, to write a part ofa machine code representation of the guest instruction to apredetermined location accessible to the computer security program, tosuspend the execution of the guest instruction, and in response tosuspending the execution of the guest instruction, to switch toexecuting the computer security program.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and advantages of the present invention willbecome better understood upon reading the following detailed descriptionand upon reference to the drawings where:

FIG. 1 shows an exemplary hardware configuration of a host computersystem according to some embodiments of the present invention.

FIG. 2-A shows an exemplary set of virtual machines exposed by ahypervisor executing on the host system, and a computer security module(CSM) protecting the set of virtual machines according to someembodiments of the present invention.

FIG. 2-B shows an alternative embodiment of the present invention,wherein a CSM executes below a virtual machine, and wherein an exceptionhandler executes within the protected virtual machine.

FIG. 2-C shows yet another embodiment of the present invention, whereinboth the CSM and the exception handler execute within the protectedvirtual machine.

FIG. 3 shows an exemplary configuration of virtualized hardware exposedas a guest virtual machine according to some embodiments of the presentinvention.

FIG. 4 shows a set of exemplary memory address translations in ahardware virtualization configuration as shown in FIG. 2-A, according tosome embodiments of the present invention.

FIG. 5 shows exemplary components of a processor according to someembodiments of the present invention.

FIG. 6 shows an exemplary suspend event register of the processoraccording to some embodiments of the present invention.

FIG. 7 shows an assembly language representation of an exemplaryprocessor instruction of the x86 instruction set, and its correspondingmachine code representation.

FIG. 8 shows an exemplary sequence of steps performed by the processorto execute a processor instruction according to some embodiments of thepresent invention.

FIG. 9 illustrates an exemplary sequence of steps performed by acomputer security module to protect a guest virtual machine according tosome embodiments of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the following description, it is understood that all recitedconnections between structures can be direct operative connections orindirect operative connections through intermediary structures. A set ofelements includes one or more elements. Any recitation of an element isunderstood to refer to at least one element. A plurality of elementsincludes at least two elements. Unless otherwise required, any describedmethod steps need not be necessarily performed in a particularillustrated order. A first element (e.g. data) derived from a secondelement encompasses a first element equal to the second element, as wellas a first element generated by processing the second element andoptionally other data. Making a determination or decision according to aparameter encompasses making the determination or decision according tothe parameter and optionally according to other data. Unless otherwisespecified, an indicator of some quantity/data may be the quantity/dataitself, or an indicator different from the quantity/data itself. Acomputer program is a sequence of processor instructions carrying out atask. Computer programs described in some embodiments of the presentinvention may be stand-alone software entities or sub-entities (e.g.,subroutines, libraries) of other computer programs. Unless otherwisespecified, a computer security program is a computer program thatprotects equipment and data against unintended or unauthorized access,modification or destruction. Unless otherwise specified, a process is aninstance of a computer program, such as an application or a part of anoperating system, and is characterized by having at least an executionthread and a virtual memory space assigned to it, wherein a content ofthe respective virtual memory space includes executable code. Unlessotherwise specified, a page represents the smallest unit of virtualmemory that can be individually mapped to a physical memory of a hostsystem. The term “logic” encompasses hardware circuitry having a fixedor a reconfigurable functionality (e.g., field-programmable gate arraycircuits), but does not encompass software emulating such functionalityon a general-purpose computer. Unless otherwise specified, a registerrepresents a storage component integrated with or forming part of aprocessor, and distinct from random-access memory (RAM). Computerreadable media encompass non-transitory media such as magnetic, optic,and semiconductor storage media (e.g. hard drives, optical disks, flashmemory, DRAM), as well as communication links such as conductive cablesand fiber optic links. According to some embodiments, the presentinvention provides, inter alia, computer systems comprising hardware(e.g. one or more processors) programmed to perform the methodsdescribed herein, as well as computer-readable media encodinginstructions to perform the methods described herein.

The following description illustrates embodiments of the invention byway of example and not necessarily by way of limitation.

FIG. 1 shows an exemplary hardware configuration of a host system 10according to some embodiments of the present invention. Host system 10may represent a corporate computing device such as an enterprise server,or an end-user device such as a personal computer, tablet computer, orsmartphone. Other exemplary host systems include TVs, game consoles,wearable computing devices, or any other electronic device having amemory and a processor. Host system 10 may be used to execute a set ofsoftware applications, such as a browser, a word processing application,and an electronic communication (e.g., email, instant messaging)application, among others. In some embodiments, host system 10 isconfigured to support hardware virtualization and to expose a set ofvirtual machines, as shown below.

FIG. 1 illustrates a computer system; the hardware configuration ofother host systems, such as smartphones and tablet computers, maydiffer. System 10 comprises a set of physical devices, including aprocessor 12, a memory unit 14, a set of input devices 16, a set ofoutput devices 18, a set of storage devices 20, and a set of networkadapters 22, all connected by a controller hub 24. In some embodiments,processor 12 comprises a physical device (e.g. multi-core integratedcircuit formed on a semiconductor substrate) configured to executecomputational and/or logical operations with a set of signals and/ordata. In some embodiments, such logical operations are delivered toprocessor 12 in the form of a sequence of processor instructions (e.g.machine code or other type of software). Some embodiments of the presentinvention introduce changes to the structure and functionality of aconventional processor, the respective changes enabling processor 12 tooperate more efficiently in hardware virtualization configurations.

Memory unit 14 may comprise volatile computer-readable media (e.g. RAM)storing data/signals accessed or generated by processor 12 in the courseof carrying out instructions. Input devices 16 may include computerkeyboards, mice, and microphones, among others, including the respectivehardware interfaces and/or adapters allowing a user to introduce dataand/or instructions into host system 10. Output devices 18 may includedisplay devices such as monitors and speakers, among others, as well ashardware interfaces/adapters such as graphic cards, allowing host system10 to communicate data to a user. In some embodiments, input devices 16and output devices 18 may share a common piece of hardware, as in thecase of touch-screen devices. Storage devices 20 includecomputer-readable media enabling the non-volatile storage, reading, andwriting of processor instructions and/or data. Exemplary storage devices20 include magnetic and optical disks and flash memory devices, as wellas removable media such as CD and/or DVD disks and drives. The set ofnetwork adapters 22 enables host system 10 to connect to a computernetwork and/or to other devices/computer systems. Controller hub 24generically represents the plurality of system, peripheral, and/orchipset buses, and/or all other circuitry enabling the communicationbetween processor 12 and devices 14, 16, 18, 20 and 22. For instance,controller hub 24 may include a memory management unit (MMU), aninput/output (I/O) controller, and an interrupt controller, amongothers. In another example, controller hub 24 may comprise a northbridgeconnecting processor 12 to memory 14 and/or a southbridge connectingprocessor 12 to devices 16, 18, 20, and 22. In some embodiments, partsof controller hub (such as the MMU) may be integrated with processor 12,i.e., may share a common substrate with processor 12.

FIG. 2-A shows an exemplary functional configuration according to someembodiments of the present invention, wherein host system 10 useshardware virtualization technology to operate a set of guest virtualmachines 52 a-b exposed by a hypervisor 50. Such configurations arecommon in applications such as cloud computing and server consolidation,among others. A virtual machine (VM) is known in the art as anabstraction, e.g., a software emulation, of an actual physicalmachine/computer system, the VM capable of running an operating systemand other software. In some embodiments, hypervisor 50 includes softwareconfigured to create or enable a plurality of virtualized devices, suchas a virtual processor and a virtual controller hub, and to present suchvirtualized devices to software in place of the real, physical devicesof host system 10. Such operations of hypervisor 50 are commonly knownin the art as exposing a virtual machine. In some embodiments,hypervisor 50 allows a multiplexing (sharing) by multiple virtualmachines of hardware resources of host system 10. Hypervisor 50 mayfurther manage such multiplexing so that each guest VM 52 a-b operatesindependently and is unaware of other VMs executing concurrentlyexecuting on host system 10. Examples of popular hypervisors include theVMware vSphere™ from VMware Inc. and the open-source Xen hypervisor,among others.

Each VM 52 a-b may execute a guest operating system (OS) Ma-b,respectively. A set of exemplary applications 56 a-d genericallyrepresent any software application, such as word processing, imageprocessing, media player, database, calendar, personal contactmanagement, browser, gaming, voice communication, data communication,and anti-malware applications, among others. Operating systems Ma-b maycomprise any widely available operating system such as MicrosoftWindows®, MacOS®, Linux®, iOS®, or Android™, among others. Each OS Ma-bprovides an interface between applications executing within therespective VM and the virtualized hardware devices of the respective VM.In the following description, software executing on a virtual processorof a virtual machine is said to execute within the respective virtualmachine. For instance, in the example of FIG. 2-A, applications 56 a-bare said to execute within guest VM 52 a, while applications 56 c-d aresaid to execute within guest VM 52 b. In contrast, hypervisor 50 is saidto execute outside, or below, guest VMs 52 a-b.

FIG. 3 shows an exemplary configuration of a virtual machine 52, asexposed by hypervisor 50. VM 52 may represent any of VMs 52 a-b of FIG.2-A. VM 52 includes a virtualized processor 112, a virtualized memoryunit 114, virtualized input devices 116, virtualized output devices 118,virtualized storage 120, virtualized network adapters 122, and avirtualized controller hub 124. Virtualized processor 112 comprises anemulation of at least some of the functionality of processor 12, and isconfigured to receive for execution processor instructions forming partof software such as an operating system and other applications. Softwareusing processor 112 for execution is deemed to execute within virtualmachine 52. In some embodiments, virtualized memory unit 114 comprisesaddressable spaces for storing and retrieving data used by virtualizedprocessor 112. Other virtualized devices (e.g., virtualized input,output, storage, etc.) emulate at least some of the functionality of therespective physical devices of host system 10. Virtualized processor 112may be configured to interact with such virtualized devices as it wouldwith the corresponding physical devices. For instance, softwareexecuting within VM 52 may send and/or receive network traffic viavirtualized network adapter(s) 122. In some embodiments, hypervisor 50may expose only a subset of virtualized devices to VM 52 (for instance,only virtualized processor 112, virtualized memory 114, and parts of hub124). Hypervisor 50 may also give a selected VM exclusive use of somehardware devices of host system 10. In one such example, VM 52 a (FIG.2-A) may have exclusive use of input devices 16 and output devices 18,but lack a virtualized network adapter. Meanwhile, VM 52 b may haveexclusive use of network adapter(s) 22. Such configurations may beimplemented, for instance, using VT-d® technology from Intel®.

Modern processors implement a hierarchy of processor privilege levels,also known in the art as protection rings. Each such ring or level ischaracterized by a set of actions and/or processor instructions thatsoftware executing within the respective ring is allowed to carry out.Exemplary privilege levels/rings include user mode (ring 3) and kernelmode (ring 0). Some host systems configured to support hardwarevirtualization may include an additional ring with the highest processorprivileges (e.g., ring −1, root mode, or VMXroot on Intel® platforms).In some embodiments, hypervisor 50 takes control of processor 12 at themost privileged level (ring −1), thus creating a hardware virtualizationplatform exposed as a virtual machine to other software executing onhost system 10. An operating system, such as guest OS Ma in FIG. 2-A,executes within the virtual environment of the respective VM, typicallywith lesser processor privilege than hypervisor 50 (e.g., in ring 0 orkernel mode). Common user applications, such as 56 a-b, typicallyexecute at lesser processor privilege than OS 34 a (e.g., in ring 3 oruser mode). Some parts of applications 56 a-b may execute at kernelprivilege level, while some parts of OS 34 a may execute in user mode(ring 3). When a software object attempts to execute an action orinstruction requiring processor privileges higher than allowed by itsassigned protection ring, the attempt typically generates a processorevent, such as an exception or a fault, which transfers control ofprocessor 12 to an entity (e.g., handler routine) executing in a ringwith enough privileges to carry out the respective action.

In particular, an attempt to perform certain actions or to executecertain instructions from within a guest VM may trigger a specialcategory of processor events, herein generically termed VM suspendevents. In some embodiments, a VM suspend event suspends execution ofthe current thread within a guest VM and switches processor 12 toexecuting a handler routine. Exemplary VM suspend events include, amongothers, a VM exit event (e.g., VMExit on Intel® platforms) and avirtualization exception (e.g. #VE on Intel® platforms). VM exit eventsswitch processor 12 to executing a handler routine outside therespective guest VM, typically at the level of hypervisor 50.Virtualization exception may switch processor 12 to executing a handlerroutine within the respective guest VM, instead of exiting therespective VM.

Exemplary instructions triggering a VM suspend event include VMCALL onIntel® platforms. VM suspend events may also be triggered by otherevents, such as memory access violations. In one such example, when asoftware object executing within a VM attempts to write to a section ofmemory marked as non-writable, or to execute code from a section ofmemory marked as non-executable, processor 12 may generate a VM exitevent. Such VM-switching mechanisms allow, for example, a computersecurity program to protect a virtual machine from outside therespective VM. The computer security program may intercept VM exitevents occurring in response to certain actions performed by softwarerunning inside the VM, actions which may be indicative of a securitythreat. The computer security program may then block and/or furtheranalyze such actions, potentially without the knowledge of in-VMsoftware. Such configurations may substantially strengthen computersecurity.

In some embodiments (e.g., FIG. 2-A), hypervisor 50 includes a computersecurity module (CSM) 60, configured to perform such computer securityoperations, among others. Module 60 may be incorporated into hypervisor50 (for instance as a library), or may be delivered as a computerprogram distinct and independent from hypervisor 50, but executing atthe privilege level of hypervisor 50. A single module 60 may beconfigured to protect multiple guest VMs executing on host system 10.Security operations carried out by module 60 may include detecting anaction performed by a process executing within a guest VM (e.g., callingcertain functions of the OS, accessing a registry of the OS, downloadinga file from a remote location, writing data to a file, etc.). Othersecurity operations of module 60 may comprise determining an address ofa memory section containing a part of a software object executing withina guest VM, accessing the respective memory section, and analyzing acontent stored within the respective memory section. Other examples ofsecurity operations include intercepting and/or restricting access tosuch memory sections, e.g., preventing the over-writing of code or databelonging to a protected process, and preventing the execution of codestored in certain memory pages. In some embodiments, CSM 60 includes aVM exit event handler 61 configured to intercept VM exit eventsoccurring within guest VMs 52 a-b. In an alternative embodiment, handler61 may be a distinct module (e.g., a library) of hypervisor 50, separatefrom CSM 60, which intercepts VM exit events and selectively transferscontrol to CSM 60 after determining a reason and/or a type of each VMexit that occurred.

FIG. 2-B illustrates an alternative embodiment wherein computer securitymodule 60 protects a guest VM 52 c from outside the respective VM. Insuch embodiments, processor 12 may be configured to generate avirtualization exception (instead of a VM exit event, as described abovein relation to FIG. 2-A) when a memory access violation occurs. In theexemplary embodiment of FIG. 2-B, a virtualization exception handler 63executes within VM 52 c, for instance at the privilege level of anoperating system Mc, and is configured to intercept virtualizationexceptions and interface with CSM 60.

Communication between handler 63 and CSM 60 may proceed according to anyinter-process communication method known in the art. To transmit datafrom within the protected VM to the level of hypervisor 50, someembodiments of handler 63 use a specialized instruction (e.g., VMCALL onIntel® platforms) to transfer control of processor 12 from therespective VM to hypervisor 50. The data being transmitted may be placedby exception handler 63 in a predetermined section of memory shared withCSM 60. To transmit data to handler 63, some embodiments of CSM 60 mayinject an interrupt into VM 52 c, the interrupt handled by handler 63.The respective data may be transferred again through the shared memorysection described above.

In yet another embodiment, illustrated in FIG. 2-C, both CSM 60 andhandler 63 execute within the protected VM, for instance in kernel mode(ring 0). Such embodiments may also employ virtualization exceptions todetect memory access violations. Deciding between configurations 2-A-B-Cmay comprise evaluating a trade-off between performance and security. VMexit events are relatively costly in terms of computation, typicallyrequiring loading and/or unloading of large data structures into/frommemory with each exit and re-entry cycle. Hence, configurations such as2-A may require more computation to intercept an event thanconfigurations such as 2-B-C. On the other hand, keeping criticalsecurity components such as CSM 60 and handlers 61-63 outside theprotected VM (as in examples 2-A-B) may strengthen security, since itmay be more difficult for malware executing within the respective VM tointerfere with the operation of such components.

To be able to protect a guest VM in a configuration as illustrated inFIGS. 2-A-B (i.e., from outside the respective VM), some embodiments ofCSM 60 employ address translation data structures and/or addresstranslation mechanisms of processor 12. Virtual machines typicallyoperate with a virtualized physical memory (see, e.g., memory 114 inFIG. 3), also known in the art as guest-physical memory. Virtualizedphysical memory comprises an abstract representation of the actualphysical memory 14, for instance as a contiguous space of addresses,commonly termed guest-physical addresses (GPA). Each such address spaceis uniquely attached to a guest VM, with parts of said address spacemapped to sections of physical memory 14 and/or physical storage devices20. In systems configured to support virtualization, such mapping istypically achieved using hardware-accelerated, dedicated data structuresand mechanisms controlled by processor 12, known as second level addresstranslation (SLAT). Popular SLAT implementations include extended pagetables (EPT) on Intel® platforms, and rapid virtualization indexing(RVI)/nested page tables (NPT) on AMD® platforms. In such systems,virtualized physical memory may be partitioned in units known in the artas pages, a page representing the smallest unit of virtualized physicalmemory individually mapped to physical memory via mechanisms such asEPT/NPT, i.e., mapping between physical and virtualized physical memoryis performed with page granularity. All pages typically have apredetermined size, e.g., 4 kilobytes, 2 megabytes, etc. Thepartitioning of virtualized physical memory into pages is usuallyconfigured by hypervisor 50. In some embodiments, hypervisor 50 alsoconfigures the SLAT structures, and therefore configures addresstranslation between physical memory and virtualized physical memory.Such address translations are known in the art as guest-physical tohost-physical (GPA-to-HPA) translations.

In some embodiments, the operating system executing within a VM sets upa virtual memory space for each process executing within the respectiveVM, said virtual memory space representing an abstraction of physicalmemory. Process virtual memory typically comprises a contiguous space ofaddresses, commonly known in the art as guest-virtual addresses (GVA) orguest-linear addresses (GLA). In some embodiments, process virtualmemory spaces are also partitioned into pages, such pages representingthe smallest unit of virtual memory individually mapped by the OS to thevirtualized physical memory of the respective VM, i.e., virtual tovirtualized-physical memory mapping is performed with page granularity.The OS may configure a dedicated data structure, such as a page table,used by the virtualized processor of the respective VM to perform guestvirtual to guest physical, or GVA-to-GPA address translations.

FIG. 4 illustrates an exemplary memory address translation in theembodiment of FIG. 2-A. Following exposure by hypervisor 50, guest VM 52a sees a virtualized physical memory space 114 a as its own physicalmemory space. A process executing within guest VM 52 a is assigned avirtual memory space 214 a by guest OS Ma. When the process attempts toaccess memory at a guest-virtual address 62, GVA 62 is translated by the(virtualized) MMU of guest VM 52 a into a guest-physical address 64within virtualized physical memory space 114 a. GVA-to-GPA translation70 a may proceed, for instance, according to page tables configured andcontrolled by guest OS 34 a. GPA 64 is further mapped by the MMU to ahost-physical address (HPA) 66 within physical memory 14 of host system10. GPA-to-HPA translation 70 b may proceed, for instance, according toSLAT structures configured by hypervisor 50.

Each process executing below guest VMs 52 a-b is typically assigned avirtual memory space addressable via what is known in the art ashost-virtual addresses (HVA). In the example of FIG. 4, hypervisor 50sets up a virtual memory space 214 b for computer security module 60.CSM 60 may then reference HPA 66 via a HVA 68. When module 60 isintegrated within hypervisor 50, for instance as a library, memory space214 b may coincide with the virtual memory space of hypervisor 50. Tomanage such spaces, hypervisor 50 may configure dedicated datastructures and mechanisms (e.g. page tables) used by the MMU to performHVA-to-HPA translations such as translation 70 c.

In some embodiments, hypervisor 50 and/or CSM 60 may set accesspermissions for each of a subset of physical memory pages. Such memorypages may be used, for instance, by certain critical guest processesexecuting within a protected VM, such as processes of the OS and/oranti-malware routines. Access permissions indicate, for instance,whether the respective page may be read from and written to, and whethersoftware is allowed to execute code from the respective page. Accesspermissions may be indicated, for instance, as a part of the SLAT entryrepresenting the respective memory page. Some host systems may allowsetting access permissions with sub-page granularity.

Hypervisor 50 and/or CSM 60 may further configure processor 12 togenerate a VM suspend event when software executing within a guest VMattempts to access memory in a manner that violates access permissions(e.g., to write to a memory page marked as non-writable). Such anattempt is hereby termed memory access violation. The respective VMsuspend event may be a VM exit event in configurations such as FIG. 2-A,and a virtualization exception in configurations such as FIGS. 2-B-C.

Some embodiments of the present invention introduce changes to thestructure and functionality of a conventional hardware processor, toenable the processor to function more efficiently in hardwarevirtualization configurations. FIG. 5 shows exemplary hardwarecomponents of processor 12 according to some embodiments of the presentinvention. The illustrated components are meant as generic devicesperforming the described functionality; structural details may varysubstantially among implementations. For instance, each illustratedcomponent may comprise multiple interconnected subsystems, notnecessarily in physical proximity to each other. The illustratedcomponents are not exhaustive; processor 12 may include many othercomponents (e.g., scheduler, interrupt controller, various caches,etc.), which were omitted from FIG. 5 to simplify presentation.

Processor 12 may include logic/circuitry configured to carry out variousstages of a processor pipeline. For instance, an instruction decoder 30performs instruction decoding operations, which may include translatingeach processor instruction into a set of elementary processor operationsand/or micro-ops. A set of execution units 36 connected to decoder 30may perform the execution stage of the pipeline. Exemplary executionunit(s) 36 include, among others, an arithmetic logic unit (ALU) and afloating-point unit (FPU).

In some embodiments, the execution stage of the pipeline for aninstruction comprises determining a result of applying an operator ofthe respective instruction to an operand of the respective instruction.Such results may comprise, among others, a memory address, a value to becommitted to a memory address or to a processor register (e.g., to ageneral purpose register such as AX, a model-specific register—MSR, acontrol register such as EFLAGS, or a hidden register such as the hiddenpart of an x86 segment register, also known as a descriptor cache), avalue of the instruction pointer (e.g., RIP), and a value of the stackpointer (e.g., RSP).

The operand(s) of an instruction may be explicit in the statement of theinstruction, or may be implicit. An exemplary x86 instruction withimplicit operands is the STC instruction, which sets the carry flag ofthe EFLAGS control register of the processor to 1. In some embodiments,the register EFLAGS and the value 1 are interpreted as (implicit)operands, although they do not appear explicitly in the statement of theSTC instruction.

A commit unit 38 may perform the commit stage of the pipeline, i.e., tostore the output of execution unit(s) 36 in memory 14 and/or to updatethe contents of certain processor registers to reflect changes/resultsproduced by the execution stage. Commit unit 38 may comprise logicmodules known in the art as retirement units.

A memory access module 34 connected to decoder 30 and execution unit(s)36 includes logic configured to interface with memory 14, e.g., to fetchinstructions from memory, to load data from memory, and to store resultsof execution of processor instructions to memory. In some embodiments,memory access module comprises an MMU configured to perform thevirtual-to-physical address translations necessary for memory access.

Modern processors typically support out-of-order and/or speculativeexecution of processor instructions. In such systems, multipleinstructions are concurrently fetched, decoded, and executed by the sameexecution unit(s) 36. Results of such executions are then committedin-order, to preserve the intended flow of the respective computerprogram. Such configurations are used, for instance, in conjunction withbranch prediction algorithms, to enhance the performance of processor12. In some embodiments configured for out-of-order execution, processor12 may further comprise a dispatcher unit 32 coupled to decoder 30 andto execution units 36, and a register file 40 coupled to executionunit(s) 36 and commit unit 38. Dispatcher unit 36 may scheduleindividual micro-ops for execution, and maintain a mapping associatingeach micro-op with its respective instruction, to control the order ofexecution and commit. Register file 40 comprises an array of internalprocessor registers, organized, for instance, as a reorder buffer.Register file 40 may further comprise logic enabling dispatcher unit 36to associate a row of registers of file 40 to each scheduled micro-op,an operation known in the art as register renaming. In suchconfigurations, each such row of registers may hold, for instance, thevalues of the general purpose and/or status registers of processor 12,said values corresponding to an intermediate stage of execution of acertain processor instruction.

Processor 12 may further include a virtual machine control unit 38configured to manage virtual machine state data. In some embodiments, avirtual machine state object (VMSO) comprises a data structure usedinternally by processor 12 to represent the current state of eachvirtualized processor exposed on host system 10. Exemplary VMSOs includethe virtual machine control structure (VMCS) on Intel® platforms, andthe virtual machine control block (VMCB) on AMD® platforms. VMSOs aretypically set up by hypervisor 50 as part of exposing each virtualmachine. In some embodiments, processor 12 associates a region in memorywith each VMSO, so that software may reference a specific VMSO using amemory address or pointer (e.g., VMCS pointer on Intel® platforms).

Each VMSO may comprise a guest state area and a host state area, theguest state area holding the CPU state of the respective guest VM, andthe host state area storing the current state of hypervisor 50. In someembodiments, the guest-state area of the VMSO includes contents of thecontrol registers (e.g., CR0, CR3, etc.), instruction pointer (e.g.,RIP), general-purpose registers (e.g., EAX, ECX, etc.), and statusregisters (e.g., EFLAGS) of the virtual processor of the respectiveguest VM, among others. The host state area of the VMSO may include apointer (e.g., an EPT pointer on Intel® platforms) to a SLAT datastructure configured for GPA-to-HPA address translations for therespective guest VM.

In some embodiments, processor 12 may store a part of a VMSO withindedicated internal registers/caches, while other parts of the respectiveVMSO may reside in memory. At any given time, at most one VMSO (hereintermed the current VMSO) may be loaded onto the processor, identifyingthe virtual machine currently having control of processor 12. Modernprocessors are typically configured for multithreading. In suchconfigurations, physical processor 12 may operate a plurality of cores,each core further comprising multiple logical processors, wherein eachlogical processor may process an execution thread independently of, andconcurrently with, other logical processors. Multiple logical processorsmay share some hardware resources, for instance, a common MMU. In amultithreaded embodiment, a distinct VMSO may be loaded onto eachdistinct logical processor.

When processor 12 switches from executing the respective VM to executinghypervisor 50 (e.g., upon a VM exit), processor 12 may save the state ofthe respective VM to the guest state area of the current VMSO. Whenprocessor 12 switches from executing a first VM to executing a secondVM, the VMSO associated to the first VM is unloaded, and the VMSOassociated to the second VM is loaded onto the processor, the secondVMSO becoming the current VMSO. In some embodiments, suchloading/unloading of VMSO data to/from processor 12 is performed byvirtual machine control module 38. Module 38 may further carry out theretrieval and/or saving of VMSO data from/to memory 14.

In some embodiments, processor 12 further comprises a suspend eventregister 44 connected to execution unit(s) 36 and/or to commit unit 38,and configured to store instruction-specific data associated with aguest instruction, wherein execution of said guest instructions hascaused a VM suspend event (e.g., a VM exit or a virtualizationexception). In some embodiments, suspend event register 44 is an exposedregister, accessible to software executing on host system 10, i.e., datastored in register 44 may be readable by software such as securitymodule 60. In one such example, suspend event register 44 includes amodel-specific register (MSR) of processor 12. Some embodiments mayrestrict access to register 44 to a subset of software objects, selectedaccording to a criterion such as processor privilege (e.g., only ring −1or root mode) or object type (e.g., only drivers). Some embodiments mayrestrict software access to register 44 only to a subset of operations(e.g., read only).

FIG. 6 shows an exemplary set of fields of suspend event register 44according to some embodiments of the present invention. Register 44 mayinclude a disassembly field 46 a and an execution result field 46 b.Disassembly field 46 a may store data resulting from disassembling therespective guest instruction.

FIG. 7 shows an assembly language representation 45 of an exemplaryIntel® x86 processor instruction. The illustrated instruction instructsthe processor to increment the content stored in memory at the (virtual)address EBX+4*ECX+0x02, by the value currently stored in register AX.The respective instruction is represented in memory as a machine code47; the translation between representations 45 and 47 is typically doneby a compiler or assembler. Machine code representation 47 has a genericform 48, comprising a sequence of encoding fields 49 a-f, which arespecific to each ISA and/or to each family of processors. On Intel®processors, such encoding fields include Prefix, Opcode, Mod R/M, SIB,Displacement, and Immediate fields. FIG. 7 shows the instance of eachencoding field for the given exemplary x86 instruction. In some ISAs,machine code representation 47 may have variable length, for instance,some encoding fields may appear in the machine code representation ofcertain instructions, but may not appear in the representation of otherinstructions. In the example of FIG. 7, representation 47 lacks anImmediate encoding field.

In some embodiments, disassembling an instruction comprises parsing themachine code representation of the instruction to identify individualinstruction encoding fields, such as fields 49 a-f in FIG. 7.Disassembling may further comprise extracting the content of individualencoding fields, and/or using such content to determine a set ofsemantic elements of the guest instruction. Such semantic elements mayinclude an operator (e.g., MOV, ADD, etc.) and an operand (e.g., AX,[EBX+4*ECX+0x02]) of the instruction, among others. Instructiondisassembly may be carried out, at least in part, by instruction decoder30 and/or by execution unit(s) 36.

In the example of FIG. 7, disassembling the illustrated instruction mayinclude identifying the ADD operator and/or determining according tomachine code 47 that the respective instruction has two operands, thatone of the operands is the content of the AX register, that the secondoperand is a content of memory, and determining an expression (e.g.,EBX+4*ECX+0x02) of the respective memory address. In some embodiments,disassembling the instruction further comprises computing a memoryaddress indicated by an operand of the respective instruction (e.g., thevalue of the expression EBX+4*ECX+0x02). In another example, wherein theguest instruction is a relative jump instruction (e.g., JMP $+10 on x86platforms, represented in machine code as 0xEB 0x08), disassembling theguest instruction may comprise calculating an absolute memory address ofthe destination according to the address of the guest instruction, tothe length of the guest instruction, and/or to the size of the relativejump.

In some embodiments, disassembly field 46 a of register 44 (FIG. 6) isconfigured to store a content of individual instruction encoding fieldsof the guest instruction, such as the Opcode, Mod R/M, and SIB fields.Other exemplary content of field 46 a includes an operator identifierindicating the operator of the respective instruction, and an indicatorof an operand of the respective instruction. The operand indicator mayfurther include an identifier of a processor register (e.g., AX), and aflag indicating, for instance, whether the respective operand is thecontent of a register or a content of memory. Disassembly field 46 a mayfurther comprise a memory address (e.g., GVA, GPA, and/or HPA) indicatedby an operand. The structure of disassemble field 46 a may be ISA and/orplatform-specific.

In some embodiments, execution result field 46 b of suspend eventregister 44 may store data indicative of a result of executing therespective processor instruction. Such results may include a value of astatus register (e.g., FLAGS), a value of an instruction pointer (e.g.,RIP), and a value of a general purpose register (e.g., EAX) resultingfrom executing the respective instruction. Field 46 b may furthercomprise a value to be committed to memory as a result of executing therespective instruction, a size of the respective value (e.g., byte,word, etc.) and/or a memory address where the respective value is to becommitted.

In some embodiments, execution unit(s) 36 and/or commit unit 38 may beconfigured to determine whether execution of a guest instruction causesa VM processor event (such as a VM exit of virtualization exception),and when yes, to save instruction disassembly data to suspend eventregister 44 before generating the respective event. Processor 12 may befurther configured to delay the generation of the processor event untilcompletion of the execution stage of the respective guest instruction,and to save a result of executing the respective instruction to eventregister 44 instead of committing such results to memory and/or to ageneral purpose register of processor 12. To avoid committing results ofsuch instructions, processor 12 may be configured to generate the VMprocessor event before the commit stage of the pipeline for therespective instruction. Such functionality will be further detailedbelow.

FIG. 8 shows a detailed, exemplary sequence of steps performed byprocessor 12 to execute a guest instruction according to someembodiments of the present invention. FIG. 8 shows an embodiment,wherein processor 12 is configured to generate a VM exit event inresponse to a memory access violation. A skilled artisan will appreciatethat the present description may easily be modified to cover anembodiment, which generates other VM suspend events (such as avirtualization exception) instead of a VM exit event. “Guestinstruction” is a term used herein to denote a processor instructionsforming part of a computer program executing within a guest VM, such asVMs 52 a-b in FIG. 2-A.

A step 302 attempts to fetch the guest instruction. When the fetchattempt fails, a step 303 may determine whether the failure is caused bya memory access violation (for instance, when the guest instructionresides in a memory page marked as non-executable in a SLAT structure ofthe guest VM). When no, in a step 306, processor 12 generates a VM exitevent and transfers execution to an event handler, such as handler 61 inFIG. 2-A. When failure to fetch the guest instruction is caused by amemory access violation, such a failure may be indicative of a securityprogram (e.g., anti-malware module) trying to protect a content of therespective memory page. One exemplary memory section typically protectedfrom execution in this manner stores an execution stack of a guestprocess. Marking the stack as non-executable may protect the guestprocess, for instance, from a stack exploit. In such situations, someembodiments may re-attempt to fetch the guest instruction, ignoring therespective memory access permissions (step 305). In a step 307, thefetched guest instruction is marked with a dedicated flag, to indicatethat the respective instruction was “force-fetched”, i.e., was fetchedwhile breaking memory access permissions. Processor 12 may then proceedto a step 308.

Following the fetch stage, step 308 decodes and dispatches the guestinstruction. In a step 310, the guest instruction is launched intoexecution. When executing the guest instruction satisfies a criterionfor VM exit, wherein the criterion is not related to memory access,processor 12 proceeds to a step 322 detailed below. Such VM exits may betriggered in a variety of situations. For instance, the guestinstruction may be a specialized instruction, such as VMCALL, whichautomatically trigger a VM exit event when called from within a guestVM. Another exemplary reason for VM exit, which is not related to memoryaccess, is the occurrence of a hardware event (e.g., an interrupt)during execution of the guest instruction.

When executing the guest instruction causes a memory access violation(for instance, when the guest instruction instructs the processor towrite a result to a memory page marked as non-writable), a conventionalprocessor typically suspends execution of the guest instruction, flushesthe processor pipeline(s) and generates a VM suspend event (e.g.VMExit). In contrast, in some embodiments of the present invention,execution of the guest instruction is not suspended. Instead, in a step318, the VM exit event is delayed until the execution stage of thepipeline for the guest instruction finishes. However, in someembodiments, the results of the completed execution stage are notcommitted, as would happen in conventional systems. Instead, in a step320, processor 12 may instruct commit unit 38 to store the results ofthe completed execution stage of the guest instruction in suspend eventregister 44. Such functionality may be achieved, for instance, using anactivation signal to switch commit unit 38 from committing results tomemory and/or general purpose registers of processor 12, to storingresults in register 44 when a memory access violation has occurred. Thecontrol signal may indicate whether execution of the guest instructionhas caused a memory access violation. Commit unit 38 may receive such asignal, for instance, from the MMU via memory access module 34. In someembodiments, step 320 comprises commit unit 38 retrieving a result ofexecuting the guest instruction from register file 40.

In an alternative embodiment, instead of saving execution results of theguest instruction to register 44, step 320 may save such results to adedicated memory region, such as the guest state area of the VMSO of therespective guest VM. In yet another embodiment, processor 12 maytransmit such results to VM exit handler 61 upon executing the VM exit(step 306).

In a step 322, processor 12 may store data resulting from disassemblingthe guest instruction to suspend event register 44 (and/or to memory asdescribed above). In some embodiments, step 322 includes writing acontent of an individual encoding field of the guest instruction toregister 44. Instruction disassembly data may be produced by instructiondecoder 30 and/or execution unit(s) 36 in the process of decoding and/orexecuting the guest instruction; step 322 may include retrieving suchdata from the respective processor module. After storing executionresults and/or disassembly data for the guest instruction, processor 12may generate a VM exit event (step 306).

When execution of the current guest instruction proceeds without causingmemory access violations (step 314) and without non-memory relatedreasons for a VM exit (step 312), a step 315 may determine whether thecurrent guest instruction was force-fetched (see steps 305-307 above).When no, a step 316 commits results of the execution to memory and/or togeneral purpose processor registers. When the current guest instructionis force-fetched, some embodiments may treat the respective instructionas an instruction causing a memory access violation, i.e., by waitingfor the respective instruction to complete the execution stage of thepipeline, storing results and/or instruction disassembly data toregister 44, before generating a VM exit event (see steps318-320-322-306 above).

FIG. 9 shows an exemplary sequence of steps performed by a guest VMand/or by computer security module 60 (FIGS. 2-A-B) according to someembodiments of the present invention related to computer security. Aguest process, such as an application (e.g., 56 a in FIG. 2-A) or aprocess of the operating system (e.g., guest OS 54 a in FIG. 2-A) mayexecute within the guest VM, advancing stepwise through a sequence ofguest instructions (step 332). Execution of the guest process continuesuntil a VM exit is generated, according, for instance, to a scenariodescribed above in relation to FIG. 8. A skilled artisan may appreciatehow the description may be adapted to a system wherein processor 12generates a virtualization exception instead of a VM exit event, andwherein an exception handler executing within the guest VM (e.g.,handler 63 in FIG. 2-B) is configured to intercept the respectiveexception.

In a step 336, handler 61 intercepts the VM exit event, which isanalyzed for evidence of a security threat. When the event indicates asecurity threat (e.g., an operation executed with malicious intent), ina step 340, CSM 60 may take protective action against the guest processand/or against the guest VM. Such action may include, among others,blocking the execution of the guest process, returning an error messageor a set of dummy results to the guest process, and alerting anadministrator of the host system.

When the VM exit event is not indicative of a security threat, a step342 determines whether the results of executing the guest instructionare available (either in event register 44 of processor 12 or inmemory). When no, CSM 60 advances to a step 348 detailed below. Whenyes, a step 344 retrieves the respective results from register 44 and/ormemory (e.g., guest state area of the VMSO of the respective guest VM).In a step 346, CSM 60 may apply the results of executing the currentguest instruction. In some embodiments, step 346 comprises a set ofoperations carried out in conventional systems at the commit stage. Forinstance, step 346 may include updating values of general purpose,control, and status processor registers of the virtualized processor ofthe respective guest VM. In some embodiments, such registers areaccessible within the guest state area of the VMSO of the respectiveguest VM. Step 346 may further include saving some results to memoryaddresses indicated by an operand of the current guest instruction. Step346 may further include incrementing the instruction pointer (e.g., RIPin x86 platforms), to show that execution of the current guestinstruction is complete.

Some embodiments of the present invention add a dedicated instruction tothe current instruction set architecture (ISA) of processor 12, the newinstruction instructing processor 12 to apply a result of execution of aguest instruction directly, from below the guest VM executing therespective guest instruction. The new instruction (an exemplary mnemonicis VMAPPLY) may carry out operations of step 346 (FIG. 9), e.g., copycontents from suspend event register 44 to virtual registers of thevirtualized processor of the respective guest VM and/or to memory.

In some embodiments, step 346 may further verify whether the currentguest instruction is an atomic instruction (e.g., as indicated by a LOCKprefix). When yes, instead of applying results directly to registers ofthe guest and/or to memory, step 346 may force a re-execution of thecurrent guest instruction upon returning to guest VM (see step 356below).

When execution results of the current guest instruction are notavailable (for instance, when the current VM exit was caused by aprivileged instruction such as VMCALL), in a step 348, computer securitymodule 60 determines whether disassembly data is available for thecurrent guest instruction. When yes, in a step 350, CSM 60 may retrievesuch data, for instance from disassembly field 46 a of register 44 (seee.g., FIG. 6). CSM 60 may then proceed to emulate the current guestinstruction according to the retrieved disassembly data (step 354).

When no disassembly data is available, a step 352 may disassemble thecurrent guest instruction before proceeding with emulation. In a step356, CSM 60 may re-launch the respective guest VM (e.g., by issuing aVMRESUME instruction on Intel® platforms). In some embodiments whereinstep 346 includes a modification of the instruction pointer, executionof the guest process will start with the processor instructionimmediately following the current guest instruction, or with a processorinstruction indicated by the current guest instruction (e.g., in thecase of control flow-changing instructions such as JMP, CALL, etc.).

The exemplary systems and methods described above allow a host system,such as a computer or a smartphone, to efficiently carry out computersecurity tasks when operating in a hardware virtualizationconfiguration. Security tasks may include, among others, protecting thehost system against malware such as computer viruses and spyware. Insome embodiments, the host system is configured to execute an operatingsystem and a set of software applications within a virtual machine. Asecurity module may execute outside the respective virtual machine, forinstance at the level of a hypervisor, and may protect the respectivevirtual machine against malware.

In some embodiments, the security module identifies a section of memory(e.g. a set of memory pages) containing code and/or data which iscritical to the security of the protected VM, and configures accesspermissions for the respective section of memory. Such accesspermissions may indicate, for instance, that the respective section ofmemory is non-writable and/or non-executable. The security module mayfurther configure the processor of the host system to generate a VMsuspend event (such as a VM exit or a virtualization exception) inresponse to a memory access violation, e.g., when software executingwithin the protected VM attempts to write to a section of memory markedas non-writable, or to execute code from a section of memory marked asnon-executable. The security module may then intercept such processorevents via an event handler, and may determine whether such events areindicative of a computer security threat. In configurations wherein thesecurity module executes outside the protected VM, the activity of thesecurity module is potentially invisible to software executing withinthe protected VM, including malware.

In conventional systems, intercepting VM suspend events proceedsaccording to methods generically known in the art as “trap-and-emulate”.In one example of a conventional technique, after determining whichinstruction caused the respective event (e.g., a VM exit), theanti-malware program emulates the respective instruction beforereturning execution to the protected VM, and modifies the instructionpointer to indicate that the respective instruction has already beenexecuted. Without the emulation step, returning execution to theprotected VM would typically re-trigger the VM exit, thus creating aninfinite loop.

Conventional trap-and-emulate systems and methods may therefore requirethe anti-malware program to include an instruction disassembler and/oran instruction emulator. Such components may be complex to develop andmaintain and may not be portable, for instance, from one processor toanother. Moreover, in conventional systems, the disassembly and/oremulation steps are typically carried out for every VM suspend event,placing a considerable computational burden onto the host system. Incontrast, some embodiments of the present invention eliminate the needfor a disassembler and/or an emulator, substantially acceleratingcomputer security operations.

Some embodiments of the present invention introduce changes to theconfiguration and operation of conventional processors, enabling suchprocessors to operate more efficiently in hardware virtualizationconfigurations.

In some embodiments, the processor is configured to, in response todetermining that a condition for generating a VM suspend event issatisfied, to save disassembly data determined for the currentlyexecuting guest instruction to a predetermined location, such as aspecific processor register or a specific memory area (e.g., the gueststate area of a virtual machine state object used by the hypervisor tomanage execution of the protected VM). Such disassembly data mayinclude, for instance, indicators of an operator and an operand of thecurrent guest instruction. In one exemplary embodiment, disassembly datacomprises contents of individual encoding fields of the guestinstruction, such as the opcode, mod R/M, and SIB fields, among others.

Such improvements may be especially beneficial for computer securityapplications, facilitating an efficient protection of a virtual machinefrom outside, e.g., from the level of a hypervisor exposing therespective VM. When compared to a conventional computer securitysolution, some embodiments of the present invention allow a substantialreduction in computation, by eliminating the instruction disassemblystage from the operation of security software configured to interceptand analyze VM exit events.

It will be clear to a skilled artisan that the above embodiments may bealtered in many ways without departing from the scope of the invention.Accordingly, the scope of the invention should be determined by thefollowing claims and their legal equivalents.

What is claimed is:
 1. A host system comprising at least one hardwareprocessor configured to execute a virtual machine and a computersecurity program, wherein the at least one processor is furtherconfigured to: determine whether executing a guest instruction withinthe virtual machine causes a violation of a memory access permission;and in response, when executing the guest instruction causes theviolation: write a part of a machine code representation of the guestinstruction to a predetermined location accessible to the computersecurity program; suspend the execution of the guest instruction; and inresponse to suspending the execution of the guest instruction, switch toexecuting the computer security program, wherein the computer securityprogram is configured to determine whether the violation is indicativeof a computer security threat.
 2. The host system of claim 1, whereinthe machine code representation comprises a sequence of encoding fields,and wherein the part comprises a content of an individual encoding fieldof the guest instruction.
 3. The host system of claim 2, wherein theindividual encoding field is selected from a group consisting of aprefix field, an opcode field, a mod R/M field, a SIB field, adisplacement field, and an immediate field of the machine coderepresentation.
 4. The host system of claim 1, wherein the part isindicative of an operator of the guest instruction.
 5. The host systemof claim 1, wherein the part is indicative of an operand of the guestinstruction.
 6. The host system of claim 1, wherein the at least onehardware processor is further configured to, in response to determiningwhether executing the guest instruction causes the violation, whenexecuting the guest instruction causes the violation, write a memoryaddress indicated by the guest instruction to the predeterminedlocation.
 7. The host system of claim 6, wherein the memory address is aguest-physical address (GPA) located within a memory space of thevirtual machine, the GPA determined by translating a virtual addressindicated by the machine code representation.
 8. The host system ofclaim 6, wherein the memory address is a host-physical address (HPA)located within a physical memory of the host system, the HPA determinedby translating a virtual address indicated by the machine coderepresentation.
 9. The host system of claim 6, wherein the memoryaddress is determined according to a memory location of the guestinstruction.
 10. The host system of claim 1, wherein the at least onehardware processor is further configured to, in response to determiningwhether executing the guest instruction causes the violation, whenexecuting the guest instruction causes the violation, write a indicatorof a processor register to the predetermined location, the registerindicated by the guest instruction.
 11. The host system of claim 1,wherein the computer security program executes within the virtualmachine.
 12. The host system of claim 1, wherein the computer securityprogram executes outside the virtual machine.
 13. The host system ofclaim 1, wherein the predetermined location comprises a predeterminedregister of the at least one hardware processor.
 14. The host system ofclaim 13, wherein the predetermined register is a model-specificregister (MSR) of the at least one hardware processor.
 15. The hostsystem of claim 1, wherein the predetermined location comprises apredetermined section of a memory of the host system.
 16. The hostsystem of claim 1, wherein the predetermined location comprises a datastructure indicative of a current state of the virtual machine.
 17. Amethod of protecting a host system from computer security threats, themethod comprising: in response to receiving a guest instruction forexecution, employing at least one hardware processor of the host systemto determine whether executing the guest instruction causes a violationof a memory access permission, wherein the guest instruction executeswithin a virtual machine exposed by the host system; and in response todetermining whether the guest instruction causes the violation, whenexecuting the guest instruction causes the violation: employing the atleast one hardware processor to write a part of a machine coderepresentation of the guest instruction to a predetermined locationaccessible to the computer security program; employing the at least onehardware processor to suspend the execution of the guest instruction;and in response to suspending the execution of the guest instruction,switching to executing a computer security program configured todetermine whether the violation is indicative of a computer securitythreat.
 18. The method of claim 17, wherein the machine coderepresentation comprises a sequence of encoding fields, and wherein thepart comprises a content of an individual encoding field of the guestinstruction.
 19. The method of claim 17, wherein the part is indicativeof an operator of the guest instruction.
 20. The method of claim 17,wherein the part is indicative of an operand of the guest instruction.21. The method of claim 17, wherein the predetermined location comprisesa predetermined register of the at least one hardware processor.
 22. Atleast one hardware processor of a host system, the at least one hardwareprocessor configurable to: in response to receiving a guest instructionfor execution, determine whether executing the guest instruction causesa violation of a memory access permission, wherein the guest instructionexecutes within a guest virtual machine exposed by the host system; andin response to determining whether the guest instruction causes theviolation, when executing the guest instruction causes the violation:write a part of a machine code representation of the guest instructionto a predetermined location accessible to the computer security program;suspend the execution of the guest instruction; and in response tosuspending the execution of the guest instruction, switch to executing acomputer security program, wherein the computer security program isconfigured to determine whether the violation is indicative of acomputer security threat.
 23. A non-transitory computer-readable mediumstoring instructions which, when executed by at least one hardwareprocessor of a host system, cause the host system to form a computersecurity program configured to determine whether a violation of a memoryaccess permission is indicative of a computer security threat, andwherein the at least one hardware processor is configurable to: inresponse to receiving a guest instruction for execution, determinewhether executing the guest instruction causes the violation, whereinthe guest instruction executes within a virtual machine exposed by thehost system; and in response to determining whether the guestinstruction causes the violation, when executing the guest instructioncauses the violation: write a part of a machine code representation ofthe guest instruction to a predetermined location accessible to thecomputer security program; suspend the execution of the guestinstruction; and in response to suspending the execution of the guestinstruction, switch to executing the computer security program.